In integrated circuits (ICs), the electrical heart beat of the circuitry is the clock signal and it regulates the pace of operation for many circuits therein. In some relatively complex ICs, such as a system-on-chip (SoC), there may be complex systems for communication between different modules of an IC (for example, a processing unit, memories, peripherals, and other dedicated units) so as to ensure observance of the specifications of performance of the system. Indeed, in certain SoC applications, some of the components may operate with different clock speeds.
In some SoC applications, the IC may include first-in-first-out (FIFO) queues between devices with different clock frequencies. For example, a FIFO queue can be set between a first device, such as a microprocessor, which writes information in the FIFO queue and a second device, such as a peripheral or a second microprocessor, which reads the information from the FIFO queue. Each device reads and writes data in the FIFO queue with a rate equal to that of its own clock. The presence of the FIFO queue serves to enable co-existence of the two domains in the SoC with different clock frequencies. The FIFO queue serves as a buffer for regulating the flow of data between devices that work at different clock speeds.
Referring to FIGS. 1-2, an approach to a FIFO memory queue 200 is now described. The FIFO memory queue 200 includes a first write logic circuit 201 operating based upon a first clock signal, a second read logic circuit 202 operating based upon a second clock signal, a memory core 203 coupled between the logic circuits, and a pointer synchronization circuit 204 also coupled between the logic circuits.
The pointer synchronization circuit 204 includes a write enable block 210 receiving a write enable signal from the first write logic circuit 201, a first binary-to-Gray encoder block 211 coupled to the write enable block, a first flip-flop block 212 coupled to the first binary-to-Gray encoder block, first and second blocks 213a-213b coupled in succession to the first flip-flop block, a first Gray-to-binary encoder block 223 coupled to the second block, and a first compare block 214 coupled to the first Gray-to-binary encoder block and outputting a FIFO empty signal. The pointer synchronization circuit 204 includes a read enable block 221 receiving a read pulse from the second read logic circuit 202, a second Gray-to-binary encoder block 222 coupled to the read enable block, a second binary-to-Gray encoder block 220 coupled to the read enable block, a second flip-fop block 219 coupled to the second binary-to-Gray encoder block, first and second blocks 218a-218b coupled in succession to the second flip-flop block, a third Gray-to-binary encoder block 217 coupled to the second block, a fourth Gray-to-binary encoder block 215 coupled to the first flip-flop block 212, and a second compare block 216 coupled to the third Gray-to-binary encoder block and outputting a FIFO full signal to the first write logic circuit 201.
In this FIFO memory queue 200, the memory core 203 is written in the first clock domain, and only one location can be pushed in the memory core in a write-domain cycle. The read domain retrieves data from the memory core 203 in the second-clock domain, one location per read-domain cycle.